1. Field of the Invention
The present invention generally relates to an analog to digital converter (A-D converter) for converting an analog signal into a digital signal. More particularly, the present invention relates to a successive approximation type A-D converter for successively comparing an analog input voltage with a comparison reference voltage on a bit-by-bit basis from the most significant bit of a digital signal.
2. Description of the Background Art
A-D converters for converting an analog signal into a digital signal are widely used in a variety of fields. Since a signal is digitally processed, high-speed, accurate signal processing can be implemented while reducing the influences such as noises. Moreover, the use of digital circuitry as processing circuitry stabilizes circuit operation and simplifies the circuit structure as much as possible.
Various circuit structures are used for such an A-D converter. A successive approximation method is conventionally known as an A-D conversion method used in the A-D converter. In this method, the bit values of the digital signal are determined by successively comparing an analog input signal with a comparison reference voltage on a bit-by-bit basis from the most significant bit. The comparison reference voltage level for the next bit value is determined according to the comparison result of the upper bit. The variation amount of the comparison reference voltage is predetermined for each comparison step. The variation amount corresponding to the weight of each respective bit of the digital signal is normally used as the variation amount of the comparison reference voltage.
FIG. 26 schematically shows an example of the structure of a conventional A-D converter. Referring to FIG. 26, the conventional A-D converter includes a ladder resistor 1 for generating a comparison reference voltage candidates through resistance division, a selector 2 for selecting an output voltage of the ladder resistor 1 in accordance with a control signal from a control circuit 100 to produce a comparison reference voltage for each comparison, a sample-and-hold circuit (S/H circuit) 3 operating under the control of control circuit 100 for sampling and holding an analog input signal (voltage) Vin, a comparator 4 for comparing the voltage held by the S/H circuit 3 with the comparison reference voltage selected by the selector 2, and a register 110 for storing an output signal of the comparator 4 successively. Register 110 outputs an n-bit digital signal D.
Control circuit 100 determines various operation timings according to a clock signal CLK from a clock generator 10, and generates a selection control signal to selector 2 according to a bit value stored in register 110. Clock generator 10 generates a basic internal clock signal CLK for determining each comparison cycle in accordance with an external clock signal. A digital conversion cycle for each analog input signal and a comparison/determination cycle for each bit value of each digital signal are determined based on this internal clock signal CLK.
Ladder resistor 1 resistance-divides externally generated or internally generated reference voltages VRT and VRB to generate candidate comparison reference voltages. The maximum output voltage value of ladder resistor 1 is a reference voltage VRTxe2x88x920.5LSB, and the minimum output voltage value thereof is a reference voltage VRB+LSB. Voltage LSB represents a resolution of A-D conversion, and corresponds to a voltage of the least significant bit of the digital signal. Provided that the digital signal is an N-bit signal, voltage LSB is given by (VRTxe2x88x92VRB)/2{circumflex over ( )}N, where the symbol xe2x80x9c{circumflex over ( )}xe2x80x9d denotes power.
FIG. 27 illustrates an example of the comparison sequence of the A-D converter shown in FIG. 26. It is herein assumed that the analog input voltage is converted into a 5-bit digital signal. The abscissa indicates time and the ordinate indicates voltage. Five conversion cycles are shown in FIG. 27. Ladder resistor 1 resistance-divides voltages the VRT and VRB and generates voltages in the range of 30.5LSB to 0.5LSB in steps of 1LSB as candidate comparison reference voltages.
In order to generate a 5-bit digital signal, ladder resistor 1 generates the voltage levels of thirty steps in accordance with the voltages VRT and VRB. Since the digital signal is a 5-bit signal, the unit variation amount (increment) of the comparison reference voltage, LSB, is given by (VRTxe2x88x92VRB)/2{circumflex over ( )}5. The minimum output voltage of ladder resistor 1 is a voltage VRB+0.5LSB, and the maximum output voltage thereof is a voltage VRB+30.5LSB. When analog input voltage Vin is higher than voltage VRB+30.5LSB, every bit of the resultant 5-bit digital signal is xe2x80x9c1xe2x80x9d. On the other hand, when analog input voltage Vin is lower than voltage VRB+0.5LSB, every bit of the resultant digital signal is xe2x80x9c0xe2x80x9d.
In the successive approximation method, each bit value of the digital signal is sequentially determined on a bit-by-bit basis from the most significant bit based on comparison between an analog input voltage and a comparison reference voltage. Therefore, comparison must be performed five times in order to generate a 5-bit digital signal.
Now, conversion operation into a 5-bit digital signal of the A-D converter shown in FIG. 26 will be described with reference to FIG. 27.
Referring to FIG. 27, it is now assumed that analog input voltage Vin is at a voltage level VRB+10LSB. S/H circuit 3 shown in FIG. 26 samples and holds this analog input voltage Vin.
In the first comparison, selector 2 selects a median of the candidate voltages output from ladder resistor 1, that is, VRB+15.5LSB, as a comparison reference voltage VC. Comparator 4 then compares analog input voltage Vin held in S/H circuit 3 with the selected comparison reference voltage VC. In the first comparison, analog input voltage Vin is lower than the comparison reference voltage. Therefore, comparator 4 outputs xe2x80x9c0xe2x80x9d and register 110 stores bit xe2x80x9c0xe2x80x9d. The first comparison result corresponds to the fifth bit (most significant bit) of the final conversion result, that is, the digital signal.
Control circuit 100 generates a control signal to selector 2 according to the value of the fifth bit (most significant bit) stored in register 110 or the output signal of comparator 4. Since comparator 4 outputs xe2x80x9c0xe2x80x9d in this stage, selector 2 selects a voltage lower than the comparison reference voltage of the first comparison by 8LSB as a comparison reference voltage of the second comparison. More specifically, in the second comparison, comparison reference voltage VRB+7.5LSB is selected and applied to comparator 4. In the second comparison, analog input voltage Vin is higher than comparison reference voltage VRB+7.5LSB. Therefore, comparator 4 outputs xe2x80x9c1xe2x80x9d and register 110 stores bit xe2x80x9c1xe2x80x9d as a value of the fourth bit.
According to the output signal of comparator 4 or the bit value stored in register 110, control circuit 100 generates such a selection control signal causing selector 2 to select a voltage higher than the comparison reference voltage of the second comparison by 4LSB, that is, VRB+11.5LSB, as a comparison reference voltage of the third comparison. In the third comparison, analog input voltage Vin is lower than the selected comparison reference voltage. Therefore, comparator 4 outputs xe2x80x9c0xe2x80x9d and register 110 stores the output signal (bit value) of comparator 4 at the position of the third bit.
According to the third comparison result, control circuit 100 generates a selection control signal such that selector 2 selects a voltage lower than the comparison reference voltage of the third comparison by 2LSB, that is, VRB+9.5LSB, as a comparison reference voltage of the fourth comparison. In the fourth comparison, analog input voltage Vin is higher than the selected comparison reference voltage VRB+9.5LSB. Therefore, comparator 4 outputs xe2x80x9c1xe2x80x9d and register 110 stores the output signal xe2x80x9c1xe2x80x9d of comparator 4 at the position of the fourth bit.
In the fifth comparison, control circuit 100 generates a selection control signal to selector 2 according to the fourth comparison result. As a result, selector 2 selects a voltage higher than the comparison reference voltage of the fourth comparison by 1LSB, that is, VRB+10.5LSB, as a comparison reference voltage of the fifth comparison. In the fifth comparison, analog input voltage Vin is lower than the selected comparison reference voltage. Therefore, comparator 4 outputs xe2x80x9c0xe2x80x9d. At the end of the fifth comparison, register 110 stores xe2x80x9c01010 (binary)xe2x80x9d, which indicates that input signal Vin is at a voltage level 10LSB on the basis of the voltage VRB. In this way, analog input voltage Vin is converted into a digital signal xe2x80x9c01010xe2x80x9d.
In the above successive approximation operation, the variation amount of the comparison reference voltage is successively varied in each comparison cycle and the variation direction thereof is determined based on the comparison result of the preceding cycle. This method is called xe2x80x9cbinary searchxe2x80x9d. In the binary search method, a target voltage level is specified by sequentially reducing the search range for a voltage of interest in decrements of xc2xd times. Since the region where the voltage of interest is present is determined in units of the voltage LSB, conversion precision is given by LSB. A coefficient for the variation amount of the comparison reference voltage in each comparison cycle corresponds to the weight of the bit value of the digital signal.
FIG. 28 schematically shows the structure of ladder resistor 1 and selector 2 in FIG. 26. Referring to FIG. 28, ladder resistor 1 includes resistive elements RA to RD connected in series with each other. Ladder resistor 1 generates a large number of comparison reference voltages, and diffused resistors or polysilicon resistors are normally used for resistive elements RA to RD. In the case where resistive elements RA to RD are formed of a diffusion layer or polysilicon, parasitic capacitance PCr to a substrate region (well region) is generated. Parasitic capacitance PCr is connected to a connection node of each resistive element.
In order that ladder resistor 1 generates a multiplicity of candidate comparison reference voltages, the resistive elements of ladder resistor 1 are connected so as to form a resistance network. FIG. 28 representatively shows resistive elements RA to RD forming a part of ladder resistor 1.
Selector 2 includes cascaded switching transistors SWPA to SWPC of a plurality of stages, and switching transistors SWNA to SWNC connected in parallel with switching transistors SWPA to SWPC respectively. P-channel MOS (insulated gate type) transistors are used for switching transistors SWPA to SWPC, and N-channel MOS transistors are used for switching transistors SWNA to SWNC. Selection control signals ZSCNA to ZSCNC are applied to the gates of switching transistors SWPA to SWPC, respectively. Selection control signals SCNA to SCNC are applied to the gates of switching transistors SWNA to SWNC, respectively.
In selector 2, P-channel and N-channel MOS transistors are connected in parallel with each other to form a so-called CMOS (Complementary MOS) transmission gate in each switching transistor. In other words, by the switching operation of the switching transistors SWPA to SWPC, SWNA to SWNC, selector 2 selects an output voltage of ladder resistor 1 as a comparison reference voltage VC without causing any loss of the threshold voltage. However, since MOS transistors are used for switching transistors SWPA to SWPC, SWNA to SWNC, parasitic capacitance PCt resulting from junction capacitance or the like is connected to each node. Moreover, channel resistance (ON-state resistance) TYr is present in the voltage transmission path.
In selector 2, a plurality of stages of switching transistors are connected in series with each other in order to reduce the parasitic capacitance to comparator 4.
As shown in FIG. 28, ladder resistor 1 has parasitic capacitance PCr at each node, and selector 2 has parasitic capacitance PCt and parasitic resistance TYr. Accordingly, upon transmission of the comparison reference voltage, RC delay due to such parasitic capacitances and parasitic resistance adversely affects the charging and discharging rates of the comparison reference voltage input node of comparator 4. More specifically, when selector 2 selects a comparison reference voltage, the voltage at the comparison reference voltage input node of comparator 4 should be rapidly set to the voltage level selected by selector 2. However, such transmission delay makes it impossible to rapidly charge or discharge the comparison reference voltage input node of comparator 4 to the voltage selected by selector 2. As a result, it takes a long time to set the voltage at the comparison reference voltage input node of comparator 4 to a required voltage level.
Moreover, as the resolution of the digital signal is increased, the number of bits of the digital signal is increased and accordingly the voltage LSB is reduced. As a result, a margin for error of the comparison reference voltage is reduced accordingly. Moreover, the number of comparison reference voltages is increased. This increases the circuit scale of ladder resistor 1 and selector 2, whereby parasitic resistance and parasitic capacitance are increased accordingly.
Accordingly, in the case of the high-resolution A-D conversion, the comparison reference voltage input node of comparator 4 may not be rapidly charged/discharged to a required voltage level in each comparison cycle.
FIGS. 29 and 30 show, in a table form, the input voltage, comparison reference voltage and comparison result of the comparison sequence of FIG. 27. Referring to FIGS. 29 and 30, the input voltage is varied in the range of 0.0LSB to 31.0LSB in increments of 1LSB. It is herein assumed that the voltage VRB is a ground voltage. The actual maximum charging/discharging amount of the input node of comparator 4 is 8LSB per conversion cycle.
When analog input voltage IN is higher than comparison reference voltage REF, xe2x80x9c1xe2x80x9d is output as the comparison result. When analog input voltage IN is lower than comparison reference voltage REF, xe2x80x9cxe2x88x921xe2x80x9d is output as the comparison result. The comparison result xe2x80x9cxe2x88x921xe2x80x9d corresponds to bit value xe2x80x9c0xe2x80x9d of the digital signal.
FIG. 29 shows the first to third comparison sequence, and FIG. 30 shows the fourth and fifth comparison results and the output results.
When the maximum charging/discharging amount of the comparison reference voltage is 8LSB per comparison cycle, the variation amount of the comparison reference voltage is equal to or smaller than the maximum charging/discharging amount in the second comparison cycle and the following comparison cycles. Therefore, an ideal comparison reference voltage (ideal value) is equal to an actual comparison reference voltage (actual value), and the output result matches the analog input voltage. As a result, A-D conversion can be performed accurately.
In FIG. 30, xe2x80x9c◯xe2x80x9d indicates that the comparison result is correct. As shown in FIG. 30, every analog input value is correctly converted into a digital signal. Provided that the comparison reference voltage input node of comparator 4 can be charged/discharged by the required amount within the comparison cycle time, A-D conversion can be performed accurately.
FIGS. 31 and 32 shows the conversion result of the case where the maximum charging/discharging amount per comparison cycle is 7LSB. FIG. 31 shows the first to third comparison results, and FIG. 32 shows the fourth and fifth comparison results and the output. In FIG. 32, xe2x80x9cXxe2x80x9d indicates that the comparison result is wrong and xe2x80x9c◯xe2x80x9d indicates that the comparison result is correct. The analog input voltage is varied in the range of 0.0LSB to 31.0LSB in increments of 1LSB.
Referring to FIG. 31, in the second comparison operation, the comparison reference voltage is actually varied by only 7LSB, although the required variation amount is 8LSB. Therefore, for analog input voltages 0.0LSB to 15.0LSB, the comparison reference voltage input node of comparator 4 is not sufficiently discharged, whereby the actual comparison reference voltage of the second comparison cycle is higher than the ideal value by 1LSB. For analog input voltages 16.0LSB to 31.0LSB, the comparison reference voltage input node of comparator 4 is not sufficiently charged, whereby the actual comparison reference voltage of the second comparison cycle is lower than the ideal value by 1LSB. As a result, in the second comparison cycle, the comparison result is wrong for analog input voltages 8.0LSB and 23.0LSB.
For the input voltages 8LSB and 23LSB, the comparison reference voltages are different in voltage level from those in the correct comparison operation in the third and following comparison cycles. As a result, the final comparison result (output) for analog input voltage 8.0LSB assumes 7LSB, and the final comparison result (output) for analog input voltage 23.0LSB assumes 24LSB.
Therefore, in the successive approximation method, an input analog signal may not be accurately converted into a digital signal on the following conditions: the maximum change rate of the comparison reference voltage to the comparison circuit is small, the actual variation amount of the comparison reference voltage is smaller than the required amount, and the difference between ideal and actual values is greater than the permissible error of the comparison reference voltage.
FIG. 33 shows an example of the relation between analog input signal Vin and comparison reference voltage VC. In FIG. 33, each comparison cycle is determined according to a clock signal CLK. In the first comparison cycle, comparison reference voltage VC is set to a median of the variable range thereof. In the first comparison cycle, comparison reference voltage VC is normally biased to a prescribed bias voltage close to the median. Therefore, comparison reference voltage VC need not be varied significantly. In other words, comparison reference voltage VC reaches the median within the comparison cycle.
It is herein assumed that comparison reference voltage VC is to be reduced by a voltage xcex94A in the following comparison cycle. As shown by dashed line in FIG. 33, if comparison reference voltage VC is actually reduced by only xcex94B due to a slow discharging rate, accurate comparison is assured as long as the difference between ideal and actual values, xcex94ER, is within the permissible error of the comparison reference voltage. However, accurate comparison and conversion would not be achieved if the difference xcex94ER exceeds the permissible error.
It is now assumed that analog input voltage Vin lies between ideal value VID and actual value VP of the comparison reference voltage, as shown in FIG. 33. If the error between ideal value VID and actual value VP, xcex94ER, is equal to or greater than the voltage LSB, there is a case that the voltage level of analog input voltage Vin would lie between actual value VP and ideal value VID. Comparison is performed according to actual value VP. Therefore, the actual comparison result is xe2x80x9c0xe2x80x9d, although the correct comparison result is xe2x80x9c1xe2x80x9d. As a result, monotonous increase in the output of the A-D converter will be impeded.
As the resolution is increased, the voltage LSB is reduced accordingly. As a result, the permissible error of comparison reference voltage VC is also reduced. In order to make comparison accuracy high, it is necessary to wait until actual value VP reaches ideal value VID. This requires an increased comparison cycle time, hindering rapid comparison.
If a wrong comparison result is obtained in one comparison cycle, the comparison reference voltages of the following comparison cycles are determined according to the wrong comparison result. As a result, a wrong conversion result would be output without compensating for the wrong bit values.
FIG. 34 shows an example of the comparison sequence. In FIG. 34, the abscissa indicates time, and the ordinate indicates voltage in units of LSB. It is herein assumed that reference voltage VRB is 0V. Analog input voltage Vin is 23LSB, and the maximum charging/discharging amount of the comparison reference voltage is less than 8LSB, and is e.g., 7LSB. The median is 15.5LSB, and input signal voltage Vin is higher than the median.
In the first comparison cycle T1, analog input voltage Vin is compared with comparison reference voltage 15.5LSB. Since analog input voltage Vin is higher than comparison reference voltage 15.5LSB, xe2x80x9c1xe2x80x9d is output.
In the second comparison cycle T2, comparison reference voltage 15.5LSB is required to be varied by 8LSB. Chain line in FIG. 34 indicates an ideal waveform of the comparison reference voltage with the variation of 8LSB. It is herein assumed that the comparison reference voltage is actually varied by the voltage xcex94B, which is equal to or less than 7LSB, due to the response delay of the waveform. Ideally, analog input signal voltage Vin is lower than the comparison reference voltage in the second comparison cycle, and therefore xe2x80x9c0xe2x80x9d should be output as the second comparison output. Actually, however, the comparison reference voltage is, e.g., 22.5LSB, which is lower than the analog input voltage Vin. Therefore, the wrong value xe2x80x9c1xe2x80x9d is output as the second comparison result.
In the third comparison cycle T3, the comparison reference voltage is further increased according to the comparison result of the second comparison cycle T2. In the third comparison cycle T3, the comparison reference voltage is varied by 4LSB with respect to the ideal comparison reference voltage of the second comparison cycle T2. Therefore, the comparison reference voltage of the second comparison cycle T2 is actually varied by (8LSBxe2x88x92xcex94B)+4LSB in the third comparison cycle T3. The maximum charging/discharging amount xcex94B is greater than the variation amount in the third comparison cycle T3, that is, 12LSBxe2x88x92xcex94B. Therefore, the comparison reference voltage can be sufficiently increased to the ideal value within the cycle time. Accordingly, the comparison result of the third comparison cycle T3 is xe2x80x9c0xe2x80x9d. In each of the following comparison cycles T4, T5, the comparison reference voltage is reduced by a prescribed value according to the comparison result, and xe2x80x9c0xe2x80x9d is output as the comparison result. As a result, xe2x80x9c11000xe2x80x9d is output as the comparison result.
If the comparison reference voltage is varied ideally, xe2x80x9c0xe2x80x9d is output in the second comparison cycle T2, and the comparison reference voltage is reduced by 4LSB in the third comparison cycle T3. Accordingly, the voltage waveform as shown by chain line in FIG. 34 is obtained in the third to fifth comparison cycles T3, T4, T5. In other words, xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9c1xe2x80x9d are respectively output as the third to fifth comparison results.
As described above, accurate conversion would be impeded if the comparison reference voltage input node of the comparator cannot be sufficiently charged/discharged, and the difference (error) between the actual comparison reference voltage and the ideal comparison reference voltage is equal to or greater than the permissible error. In FIG. 34, the analog input voltage should be converted into xe2x80x9c23 (decimal)xe2x80x9d, but is actually converted into xe2x80x9c24 (decimal)xe2x80x9d.
In the successive approximation type A-D converter, the reference voltage level of each comparison cycle is determined according to the comparison result of the preceding comparison cycle. Therefore, if an erroneous comparison result is present in any of the upper bits, it would affect the lower bits. The successive approximation type A-D converter does not have a function of correcting such an error. Therefore, as the resolution is increased and the permissible error of the comparison reference voltage is reduced, the influence of the charging/discharging rate of the comparison reference voltage is increased significantly. Such an influence is more remarkable particularly for accurate, rapid conversion.
Such a problem is not limited to the above A-D converter using a ladder resistor. An A-D converter using a capacitor and a hybrid A-D converter using both a ladder resistor and a capacitor also successively compare an input analog voltage with a comparison reference voltage in the successive approximation type A-D conversion circuitry. Therefore, such A-D converters also encounter the same problem.
It is an object of the present invention to provide a successive approximation type A-D converter capable of rapidly converting an analog signal into a digital signal with high accuracy.
It is another object of the present invention to provide a successive approximation type A-D converter having an error correction function and thus capable of generating an accurate conversion result even if a wrong comparison result is produced.
According to a first aspect of the present invention, an analog to digital (A-D) converter includes a comparator for comparing an analog signal with a comparison reference voltage a predetermined number of times that is equal to the number of bits of an output digital signal, and a control circuit for controlling the comparator to perform the predetermined number of comparisons and a redundant comparison. A voltage level of the comparison reference voltage is variable in each comparison. The control circuit determines and sets the voltage level of the comparison reference voltage in each comparison.
According to a second aspect of the present invention, an analog to digital (A-D) converter includes a comparator for comparing an applied analog signal with a comparison reference voltage, and a control circuit for setting a period of comparison cycles of the comparator and a voltage level of the comparison reference voltage in each comparison cycle. The control circuit determines the respective cycle periods of second and subsequent comparisons of such that the cycle times of successive comparison cycles including at least said second comparison cycle vary from each other.
According to the second aspect of the present invention, the A-D converter further includes a circuit for generating a digital signal corresponding to the analog signal according to an output signal of the comparator.
Such redundant comparison provides an error correction function. More specifically, even if a wrong conversion result is generated in any of the predetermined number of comparisons, the error can be corrected based on the redundant comparison result to achieve accurate analog-to-digital conversion. Moreover, since merely the redundant comparison is performed, conversion can be performed with high accuracy in synchronization with a high-speed clock signal.
The redundant comparison may be added after the predetermined number of comparisons. The successive approximation type A-D converter performs the conversion based on the binary search method. Therefore, even if a wrong conversion result is generated due to insufficient charging/discharging of the comparison reference voltage, such an increased number of comparison cycles ensures a convergence period of the conversion output to an input voltage. Accordingly, the final conversion output can be generated with the error corrected.
Alternatively, the redundant comparison may be inserted into a comparison cycle to equivalently increase the cycle time of that comparison cycle. In this case, even if comparison is made in synchronization with a high-speed clock signal and the cycle time is shortened, the comparison reference voltage can be sufficiently charged or discharged to a desired voltage level. Accurate comparison is thus ensured.
In the successive approximation type A-D converter, the second comparison cycle may have a longer cycle time than the other comparison cycles. This provides a sufficient period for the comparison reference voltage to be varied in the second comparison cycle that is the largest in variation amount of the comparison reference voltage. Therefore, even if the charging/discharging rate of the comparison reference voltage is not high enough, the comparison reference voltage can be accurately set to a desired voltage level within the cycle time. As a result, comparison for generating a digital signal can be accurately made even if a short basic cycle time is assigned to the comparison cycles.